High frequency switch-mode power amplifier

ABSTRACT

A switch-mode power amplifier circuit using high power, low distortion waveforms is connected to an electromagnetic load to provide a high degree of control over the load. The circuit comprising a plurality of half-bridge networks having outputs combined at a summation point. The half-bridge networks are switched to provide power outputs sequenced to generate an interlaced output at the summation point which is operably connected to the load so that for a given switching frequency of the networks the operational frequency of the circuit is increased. The sequencing of the half-bridge outputs to generate an interlaced output facilitates the reduction of the switching frequency of individual switching components within the half-bridges while at least maintaining the overall operational frequency of the circuit. For N half-bridges operating at fkHz, the overall operational frequency of the circuit is NfkHz. Alternatively, the switching frequency of individual switching elements of a system operating at fokHz may be reduced by a factor of N. A feedback signal generated across the load is included at the summation point and is optionally augmented to decrease distortion.

FIELD OF THE INVENTION

[0001] The present invention relates to power amplifiers adapted for driving electromagnetic loads including audio loudspeakers, motors and signal generating devices for vibration and acoustic testing. More particularly, the invention relates to switch-mode power amplifiers for use in vibration testing.

BACKGROUND OF THE INVENTION

[0002] Power amplifiers for use in driving, for example, electro-dynamic shakers must be capable of stable operation with a wide range of electrical loads, offer low distortion, make efficient use of electrical power, be compact in design and allow for computer control.

[0003] The use of switch-mode power technology in such amplifiers provides many advantages over linear amplification techniques and are available presently in a range of 5 to 300 kVA. The use of switch-mode power technology dramatically improves amplifier efficiency over linear amplifiers, thus reducing power losses. This allows air cooling of semi-conductor heatsinks, as opposed to water cooling. A reduced output semi-conductor component count for switch-mode designs increases reliability also. By using computer operation and control of switching modulations, lower total harmonic distortion figures may be established.

[0004] A standard switch-mode amplifier approach is to use a single half-bridge at high frequency (for examples 150 kHz). To reduce distortion from the amplifier a feedback path is applied. The amount of feedback which can be applied however is limited by the switching frequency of the individual switching elements. To obtain lower distortion a higher switching frequency should be used as this allows more feedback. However, in the half-bridge topology, as the switching frequency increases the losses in the power switches increase. This reduces efficiency. Specialised high frequency switching elements may be used but these are inherently expensive. Thus, a compromise is established between the cost of the high frequency switching elements allowable distortion and the output power.

[0005] It is an objective of the present invention to alleviate the disadvantages associated with prior art amplification techniques and to provide a switch-mode power amplifier having a controllable high frequency output.

SUMMARY OF THE INVENTION

[0006] Accordingly, the present invention provides a switch-mode power amplifier circuit connectable to an electromagnetic load, the circuit comprising a plurality of half-bridge networks having outputs combined for summation at a summation point, the half-bridge networks being switched to provide power outputs sequenced to generate an interlaced output at the summation point which is operably connected to the load so that for a given switching frequency of the networks the operational frequency of the circuit is increased.

[0007] The sequencing of the half-bridge outputs to generate an interlaced output facilitates the reduction of the switching frequency of individual switching components within the half-bridges while at least maintaining the overall operational frequency of the circuit. For N half-bridges operating at f kHz, the overall operational frequency of the circuit is Nf kHz. Alternatively, the switching frequency of individual switching elements of a system operating at fokHz may be reduced by a factor of N.

[0008] Preferably, a feedback path is provided so that a feedback signal is generated across the load. Most preferably, the summation of the half-bridge network outputs includes the feedback signal;

[0009] Conveniently, where the operating frequency of the circuit is increased, further feedback may be imposed on the circuit to reduce distortion.

[0010] Advantageously, the half-bridge networks are arranged in a push-pull configuration about the load. This configuration defines a left and right channel for which a power drive signal may be derived to generate timing signals for controlling individual switching elements of the half-bridge networks.

[0011] Preferably, a timing strategy is used to ensure current sharing between the networks.

[0012] Each half-bridge network comprises two switching elements in opposite switched states. Conveniently, the states are a high impedance state representing “OFF” and a low impedance state representing “ON”.

[0013] An identical supply voltage is supplied to each half-bridge network.

[0014] The switched power outputs of the half-bridge networks are provided with an inline inductance. Preferably, the inductance is identical for each output.

[0015] An output filter stage is provided on the circuit. Preferably at least part of the filter is shunt-connected across the load in use.

[0016] A current sensor is provided on the output of each half-bridge network so that a current error signal can be derived. The error signal is compared with a plurality of waveforms to give a timing signal to regulate the switching of the half-bridge switching elements.

[0017] The switching of the half-bridge switching elements is preferably controlled using Pulse Width Modulation (PWM) techniques.

[0018] The use of a plurality of power devices, operating an interlaced fashion, in order to increase the apparent operating frequency of the system, allows more feedback to be imposed on the system.

[0019] The invention is applicable to any system where high power, low distortion waveforms are required to drive a load, particularly an electromagnetic load, with a high degree of control.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The invention will now be described more particularly with reference to the accompanying drawings which show, by way of example only, two embodiments of switch-mode power amplifier according to the invention. In the drawings:

[0021]FIG. 1 is a schematic circuit diagram of a prior art standard switching amplifier incorporating a half-bridge network;

[0022]FIG. 2 is a schematic circuit diagram similar to that of FIG. 1 incorporating two half-bridge networks in a push-pull configuration;

[0023]FIG. 3 is a schematic circuit diagram of a switching amplifier according to a first embodiment of the invention incorporating three half-bridge networks;

[0024]FIG. 4 is a waveform diagram illustrating the individual and combined output currents of the half-bridge networks of FIG. 3;

[0025]FIGS. 5a and 5 b are schematic circuit diagrams of half-bridge networks showing details of the switching elements;

[0026]FIG. 6 is a schematic circuit diagram of a power stage of a switch-mode amplifier according to a second embodiment of the invention having N pairs of half-bridge networks in a push-pull configuration;

[0027]FIG. 7 is a schematic waveform diagram showing the output current I to the load for an amplifier having three pairs of half-bridge networks;

[0028]FIG. 8 is a schematic diagram of a current feedback circuit for generating an error signal; and

[0029]FIG. 9 is a schematic overview of a high frequency switch-mode power amplifier according to the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0030] Referring to the drawings and initially to the prior art arrangements of FIGS. 1 and 2, a standard switching amplifier comprising a single half-bridge is shown in FIG. 1. The switching elements S1, S2 are operated at high frequency, for example, 150 kHz, each element being in the opposite switched state to the other. If the first switching element S1 is conducting or in a low impedance mode, that is, “ON”, then the second switching element S2 is not conducting or is in a high impedance state, that is “OFF”. In the particular application considered (driving an electromagnetic load), it is important that amplifier distortion is kept to a minimum. To achieve this, feedback is applied. The amount of feedback which can be applied is limited by the switching frequency of the switching elements. An increase in the switching frequency allows more feedback to be applied and thus decreases distortion. Unfortunately, high speed switching creates heating problems, increases losses in the switches and the associated risk of component failure increases. Additionally, the high speed switching of individual components increases the incidence of radio frequency interference necessitating shielding which adds to the overall cost of the amplifier.

[0031] A push-pull configuration, as illustrated in FIG. 2, comprising a pair of half-bridges, overcomes some of the disadvantages discussed hereinabove. By adding a half-bridge comprising a usually identical pair of switching elements S3, S4 to the other side of the load, each side or channel can operate at 75 kHz giving an overall searching frequency of 150 kHz. Thus, the decreased switching speed of the switching elements S1, S2, S3, S4 ensure losses and distortion are kept to a minimum while the overall high operating frequency of the circuit allows greater feedback.

[0032] Referring now to FIG. 3, the first embodiment of the invention comprises a switch-mode power amplifier having three half-bridge networks, each operating at one third of the overall operating frequency required. The first half-bridge comprises switching elements SW₁, SW₂ generating a current profile I₁ passed through a first inductor L₁ to a summation point P. The second half-bridge comprises switching elements SW₃, SW₄ generating a current profile I₂ passed through a second inductance L₂ to the summation point P and the third half-bridge comprises usually identical switching elements SW₅, SW₄ generating a current profile I₃, passed through a third inductance L₃ to the summation point P. These profiles I₁, I₂, I³ are combined by a summation element (not shown) to give a final current profile I, as shown in FIG. 4, which is applied to the load. From this current characteristic I, which has a higher ripple frequency than any of the source current profiles I₁, I₂, I₃, it will be appreciated that substantially more feedback may be applied to this circuit to reduce distortion of the amplifier.

[0033] In the above arrangement, three half-bridges each operating at a relatively low frequency of 50 kHz results in an apparent switching frequency of 150 kHz at the load. Thus, identical amplifier performance can be achieved with lower switching losses.

[0034] It will further be appreciated that by increasing the number of half-bridge networks in this circuit, the overall operating frequency can be increased with no real overall increase in distortion and that feedback can be increased to further decrease distortion. Optionally, or concurrently, the power rating of the switching elements may be increased and their operating speeds decreased. Thus, N half-bridges operating at a switching frequency off f kHz gives an apparent switching frequency of Nf kHz. Alternatively, a required frequency of fo may be achieved by using N half-bridges operating at an Nth factor of the overall switching frequency fo.

[0035]FIGS. 5a and 5 b are illustrations of suggested switching elements in a half-bridge configuration. Any switching element suitable for relatively high speed, high power application may be used Generally, MOSFET or IGBT elements are preferred. Gate or base current is provided to the switching elements from timing circuitry (not shown) which is normally controlled using Pulse Width Modulation (PWM) techniques.

[0036] In FIG. 6, the half-bridge networks (denoted generally as ½) are arranged in a push-pull configuration with N pairs of half-bridges, one of each pair being provided on either side of the load to define a left channel and a right channel. Taking the left channel, each half-bridge has an output S which is passed through an inductance L before the output is combined at a summation point (or rail) to produce the channel output supplied to the load. The combined output of the left and right channels to the load, which has a capacitor C connected in parallel thereto, gives the system output current I. In the embodiment of the invention, each channel has three half-bridges, the left channel having switching profiles S₁, S₂, S₃ and output currents I₁, I₂, I₃, passed through inductors L₁, L₂, L₃ and the right channel has switching profiles S₄, S₅, S₆, and output currents I₄, I₅, I₆ passed through inductors L₄, L₅, L₆. The switching profiles S₁, S₂, S₃, S₄ S₅, S₆, and the system output current characteristics I are shown in FIG. 7 which is discussed in more detail hereinafter,

[0037] The amplifier topology preferred is such that it may be separated into discrete elements including the power stage, supplying the load, the voltage feedback circuit, the current feedback circuit and the PWM circuitry. The power stage of the circuitry is comprised of six identical half-bridge structures, each of which comprises two IGBT's as shown for example in FIG. 5B. In this arrangement, when the top device is “ON” (in a low impedance state), the opposing device is “OFF” (in a high impedance state), and vice versa. The supply to each half-bridge is identical and not connected to ground (earth).

[0038] The currents I₁, I₂, I₃, I₄, I₅, I₆, through the six inductors L₁, L₂, L₃, L₄, L₅, L₆ are measured by current sensors, giving signals which are then summed, as shown in FIG. 8, for comparison with a drive signal. The currents I₁, I₂, I₃ on the left channel are summed and compared to produce a “left error” signal. An identical process occurs with the currents I₄, I₅, I₆ on the opposite side, read through the corresponding inductors L₄, L₅, L₆. The current signals are summed as before for comparison but are inverted before producing the “right error” signal.

[0039] Referring now to FIG. 7, the “left error” and “right error” signals are compared, with three triangular waves T₁, T₂, T₃ which are equally spaced in time. When the left error signal exceeds the first triangular wave T₁ the output of the first half-bridge of the left channel S₁ is driven high, and when the signal falls below the triangular wave T₁ the output S₁ is driven low. This is true also for the signal profiles of the second and third triangular waves T₂, T₃ and outputs of the second and third half-bridge networks S₂, S₃, respectively. The right error signal is also compared, as shown in FIG. 7, with the same triangular waves T₁, T₂, T₃, such that when the right error signal exceeds the first triangular wave T₁, the output of the first half-bridge of the right channel S₄ is driven high. When the signal falls below the triangular wave, the output S₄ is driven low. This is also true for the relationship between the second and third triangular waves T₂, T₃, and the second and third right channel half-bridge outputs S₅, S₆, respectively.

[0040] The inductors L₁, L₂, L₃, L₄, L₅, L₆ facilitate the integration of the sum of the left channel output currents (I₁+I₂+I₃) less the sum of the right-hand output currents and the load voltage (I₄+I₅+I₆+V). This gives a smoothed output current I, as shown in FIG. 7, with transitions at every half-bridge state change. Thus, the rate of change of inductor current alters six times as often as any of the half-bridge outputs alter. The capacitor C in parallel with the load combines with the individual inductors L₁, L₂, L₃, L₄, L₅, L₆ to form a low pass filter. This ensures that little of the overall switching frequency is observed at the load.

[0041] The drive signal, shown in FIG. 8, is created by subtracting the load voltage V from the input signal. This drive signal is identical for creating both right and left current feedback signals.

[0042] There are six current transducers/sensors so the currents through each inductor are measured. In this way any imbalance in the current levels in the inductors can be calculated. If any inductor has any more current in it than the overall mean (average current), then the associated half-bridge has its timing adjusted to correct for this imbalance. This process is achieved as is the overall control strategy using a digital control method.

[0043] The overall strategy of the amplifier is shown in FIG. 9. The input signal is used to create left and right channel “drive” signals in a voltage feedback circuit. The drive signals are passed to the current feedback circuits, as illustrated in FIG. 8. The error signals are passed to timing circuits shown as “PWM strategy” which generates timing signals to the half-bridge switching elements.

[0044] If higher power levels are required than can be obtained from one set of six half-bridges then multiple units can be used. This is possible by paralleling units inside the voltage feedback loop such that each unit receives the same drive signal and is connected identically to the load. The current feedback loops ensure that all units carry identical current loads. In this way, any quantity of units may be paralleled.

[0045] It will be appreciated that at lower speeds, higher currents can be switched with greater ease. This also facilitates the use of cheaper high power switching elements. The topology of the invention facilitates production of a power amplifier having a kVA rating double that previously available at substantially the same cost. Additionally, as specified in the preferred embodiment, an amplifier with two sets of three half-bridges, each operating at 25 kHz, gives them apparent operating frequency of 150 kHz at the load. Cheaper switching elements operating at slower speeds and capable of handling high currents can be used as speeds well within their optimum range, decreasing the incidence of component failure and increasing the overall reliability of the amplifier.

[0046] Radio frequency interference is also reduced as the reduced switching frequency allows lower voltage transients (dv/dt) without substantially affecting efficiency.

[0047] The term “electromagnetic load” as used herein may be applied to audio speakers, electric motors to which high quality waveforms are to be applied and signal generating devices used in connection with vibration and acoustic testing. The invention is however more particularly directed to electro-dynamic shakers used for vibration testing.

[0048] It will of course be understood that the invention is not limited to the specific details described herein, which are given by way of example only, and that various modifications and alterations are possible within the scope of the invention. 

1. A switch-mode power amplifier circuit connectable to an electromagnetic load, the circuit comprising a plurality of half-bridge networks having outputs combined for summation at a summation point, the half-bridge networks being switched to provide power outputs sequenced to generate an interlaced output at the summation point which is operably connected to a load so that for a given switching frequency of the networks the operational frequency of the circuit is increased.
 2. A switch-mode power amplifier circuit as claimed in claim 1, in which the sequencing of the half-bridge outputs to generate an interlaced output facilitates the reduction of the switching frequency of individual switching components within the half-bridges while at least maintaining the overall operational frequency of the circuit.
 3. A switch-mode power amplifier circuit as claimed in either claim 1 or claim 2, in which, for N half-bridges operating at f kHz, the overall operational frequency of the circuit is Nf kHz.
 4. A switch-mode power amplifier circuit as claimed in either claim 1 or claim 2, in which, for N half-bridges, the switching frequency of individual switching elements of a system operating at fokHz may be reduced by a factor of N.
 5. A switch-mode power amplifier circuit as claimed in any one of the preceding claims, in which a feedback path is provided so that a feedback signal is generated across a load.
 6. A switch-mode power amplifier circuit as claimed in claim 5, in which the summation of the half-bridge network outputs includes the feedback signal.
 7. A switch-mode power amplifier circuit as claimed in either claim 5 or claim 6, in which, where the operating frequency of the circuit is increased, further feedback may be imposed on the circuit to reduce distortion.
 8. A switch-mode power amplifier circuit as claimed in any one of the preceding claims. in which the half-bridge networks are arranged in a push-pull configuration about a load, the configuration defining a left and right channel for which a power drive signal may be derived to generate timing signals for controlling individual switching elements of the half-bridge networks.
 9. A switch-mode power amplifier circuit as claimed in any one of the preceding claims, in which a timing strategy is used to ensure current sharing between the networks.
 10. A switch-mode power amplifier circuit as claimed in any one of the preceding claims, in which each half-bridge network comprises two switching components in opposite switched states.
 11. A switch-mode power amplifier circuit as claimed in claim 10, in which the states are a high impedance state representing “OFF” and a low impedance state representing “ON”.
 12. A switch-mode power amplifier circuit as claimed in any one of the preceding claims, in which an identical supply voltage is supplied to each half-bridge network.
 13. A switch-mode power amplifier circuit as claimed in any one of the preceding claims, in which the switched power outputs of the half-bridge networks are provided with an in-line inductance.
 14. A switch-mode power amplifier circuit as claimed in claim
 13. in which the inductance is identical for each output.
 15. A switch-mode power amplifier circuit as claimed in any one of the preceding claims, in which an output filter stage is provided on the circuit, at least part of which is shunt-connected across a load in use.
 16. A switch-mode power amplifier circuit as claimed in any one of the preceding claims, in which a current sensor is provided on the output of each half-bridge network so that a current error signal can be derived.
 17. A switch-mode power amplifier circuit as claimed in claim 16, in which the error signal is compared with a plurality of waveforms to give a timing signal to regulate the switching of the half-bridge switching elements.
 18. A switch-mode power amplifier circuit as claimed in any one of claims 2 to 17, in which the switching of the half-bridge switching components is controlled using Pulse Width Modulation (PWM) techniques.
 19. A switch-mode power amplifier circuit as claimed in any one of the preceding claims, in which the use of a plurality of power devices. operating an interlaced fashion, in order to increase the apparent operating frequency of the system, allows more feedback to be imposed on the system.
 20. A switching-mode power amplifier circuit as claimed in any one of the preceding claims, in which the system is used to drive a load, particularly an electromagnetic load, using high power, low distortion waveforms with a high degree of control.
 21. A switch-mode power amplifier circuit substantially as herein described with reference to and as shown in FIGS. 3 to 9 of the accompanying drawings. 